本章节以其中一个不同于Atlas 200I DK A2 开发者套件、Atlas 500 A2 智能小站的用户底板设计为例,根据底板的设计来配置对应SATA接口的userBaseConfig文件和DTB文件。
已获取设备boardid,本章节以33150为例。具体请参见用户必读。
用户底板的adc_board_id为33,Atlas 200I A2 加速模块的算力为20T(adc_board_id为150),用户整机(Atlas 200I A2 加速模块+底板)boardid为33150(对应十六进制817e)。
本操作以首次调测接口为例介绍。
su - root
cd /opt
tar -xzvf Ascend310B-source.tar.gz
cd Ascend310B-source
<item name="product_strategy_info"><!--产品板策略ID--> <!--33150 对应十六进制817e--> <param board_id ="817e" phy_num = "1" chip0_strategy="0" max_power="0" equal="0"/> </item> <item name="evb_strategy_info"> </item> <item name="strategy_info_array"><!--启动策略矩阵--> <subitem subname="sub_strategy0"> <module class="serdes"> <submodule subclass="serdes_info"> <param lan_index="0" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="2" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="1" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="2" serdes_type="SATA" ssc_enable="1" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="SATA3.0" port_index = "0"/> <param lan_index="3" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="1" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="4" serdes_type="ETH" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "1" bandwidth="ff" align_mode="0" frequency="1GE" port_index = "0"/> <param lan_index="5" serdes_type="ETH" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "1" bandwidth="ff" align_mode="0" frequency="1GE" port_index = "0"/> <param lan_index="6" serdes_type="USB" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="USB3.0" port_index = "0"/> <param lan_index="7" serdes_type="USB" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="USB3.0" port_index = "0"/> </submodule> </module>
各参数含义如下。
param |
配置值 |
说明 |
---|---|---|
lan_index |
0~7。 |
lane编号,Atlas 200I A2 加速模块一共有8条serdes lane。 |
serdes_type |
Atlas 200I A2 加速模块支持PCIE、SATA、USB、ETH。 |
该条lane使用的协议。 |
ssc_enable |
|
是否开展频a,只有用作PCIe和SATA时才能打开。 |
polarity_tx |
|
tx极性是否翻转。 |
polarity_rx |
|
rx极性是否翻转。 |
lan_order |
|
lane序是否反转。只有用作ETH时需要修改,具体请参见《Atlas 200I A2 加速模块 硬件开发指南》的“以太网接口”章节。 |
bandwidth |
|
用作PCIe时,表示位宽x4/x2/x1,其他协议不使用。
|
align_mode |
0。 |
该lane是master还是slave,Atlas 200I A2 加速模块不使用该参数。 |
frequency |
|
使用的频点b,主要用来区分PCIE GEN2/3,和ETH的1GE/2.5GE。 |
port_index |
0~n。 |
用作ETH时,表示lane的网口端口号,其他协议不使用。不使用时设置为0。 |
a:时钟展频通过频率调制的手段将集中在窄频带范围内的能量分散到设定的宽频带范围,通过降低时钟在基频和奇次谐波频率的幅度(能量),达到降低系统电磁辐射峰值的目的。 b:PCIe的频点是指数据在总线上传输的速率,也称为数据传输速度。 |
弹性配置中的SerDes复用关系参数必须与实际硬件单板保持一致,SerDes错误配置可能导致启动挂死,功能不可用。
根据表3中用户产品的实际serdes配置,为使能接口功能,user_base_config.xml文件中serdes_info配置的示例如下。
lan编号 |
协议 |
是否开展频 |
tx极性是否翻转 |
rx极性是否翻转 |
lane序是否反转 |
位宽 |
频点 |
---|---|---|---|---|---|---|---|
lane0 |
PCIE |
否 |
否 |
否 |
否 |
x2 |
PCIE_GEN2 |
lane1 |
PCIE |
否 |
否 |
否 |
否 |
不配置a |
PCIE_GEN2 |
lane2 |
SATA |
是 |
否 |
否 |
否 |
不配置 |
SATA3.0 |
lane3 |
PCIE |
否 |
否 |
否 |
否 |
x1 |
PCIE_GEN2 |
lane4 |
ETH |
否 |
否 |
否 |
是 |
不配置 |
1GE |
lane5 |
ETH |
否 |
否 |
否 |
是 |
不配置 |
1GE |
lane6 |
USB |
否 |
否 |
否 |
否 |
不配置 |
USB3.0 |
lane7 |
USB |
否 |
否 |
否 |
否 |
不配置 |
USB3.0 |
a:lane0的PCIe位宽为x2,需要使用两条lane,所以lane1不设置位宽。 |
user_base_config.xml文件中serdes_info配置如下。
<submodule subclass="serdes_info"> <param lan_index="0" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="2" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="1" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="2" serdes_type="SATA" ssc_enable="1" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="SATA3.0" port_index = "0"/> <param lan_index="3" serdes_type="PCIE" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="1" align_mode="0" frequency="PCIE_GEN2" port_index = "0"/> <param lan_index="4" serdes_type="ETH" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "1" bandwidth="ff" align_mode="0" frequency="1GE" port_index = "0"/> <param lan_index="5" serdes_type="ETH" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "1" bandwidth="ff" align_mode="0" frequency="1GE" port_index = "0"/> <param lan_index="6" serdes_type="USB" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="USB3.0" port_index = "0"/> <param lan_index="7" serdes_type="USB" ssc_enable="0" polarity_tx = "0" polarity_rx = "0" lan_order = "0" bandwidth="ff" align_mode="0" frequency="USB3.0" port_index = "0"/> </submodule>
位宽只能配置为x4/x2/x1。
cd /opt/Ascend310B-source
出现如下回显,表示编译内核userBaseConfig文件成功。
generate /opt/Ascend310B-source/output/userBaseConfig.bin success! sign /opt/Ascend310B-source/output/userBaseConfig.bin success!
编译后的“userBaseConfig.bin”文件会自动存放于“Ascend310B-source/output”目录下。
以用户整机的boardid为33150为例,故dts文件名称为“hi1910B-asic-M150-B33.dts”。具体请参见DTB文件。
cp hi1910B-asic-M150-B50.dts hi1910B-asic-M150-B33.dts
将“hi1910B-asic-M150-B50.dts”另存为boardid33150的dts文件“hi1910B-asic-M150-B33.dts”。
compatible = "hisilicon,hi1910B-evb", "hisilicon,ascend610"; hisi,boardid = <0x0 0x3 0x3 0x1 0x5 0x0>; //修改为实际整机boardid #address-cells = <0x2>; #size-cells = <0x2>; interrupt-parent = <0x1>; model = "Hisilicon PhosphorHi1910B evb"; /include/ "base/hi1910B-asic-kernel-rc.dtsi" /include/ "base/hi1910B-commmon-smmu.dtsi" /include/ "base/hi1910B-mpam.dtsi" /include/ "base/hi1910B-lp-pm.dtsi" /include/ "base/hi1910B-lp-devmng.dtsi" /include/ "base/hi1910B-mbigen-ao.dtsi" /include/ "base/hi1910B-gpio.dtsi" /include/ "base/hi1910B-ipcdrv.dtsi" /include/ "base/hi1910B-ts-drv.dtsi" /include/ "base/hi1910B-tsdrv.dtsi" /include/ "base/hi1910B-network-M150-B50.dtsi" /include/ "base/hi1910B-hidvpp.dtsi" /include/ "base/hi1910B-hdmi.dtsi" /include/ "product/hi1910B-audio.dtsi" /include/ "base/hi1910B-mipitx.dtsi" /include/ "base/hi1910B-vdp.dtsi" /include/ "base/hi1910B-isp.dtsi" /include/ "base/hi1910B-hilink.dtsi" /include/ "base/hi1910B-mntn-milanr3.dtsi" /include/ "base/hi1910B-gpu.dtsi" /include/ "base/hi1910B-ctl.dtsi" /include/ "base/hi1910B-itrustee.dtsi" /include/ "base/hi1910B-sata.dtsi" /include/ "product/hi1910B-pcie-rc-M150-B50.dtsi" //确认所使用的PCIe的.dtsi文件及路径 /include/ "product/hi1910B-mdio-M150-B50.dtsi" /include/ "product/hi1910B-pinctrl-M150-B50.dtsi" /include/ "product/hi1910B-can-M150-B50.dtsi" /include/ "product/hi1910B-hiusbc-B50.dtsi" /include/ "product/hi1910B-emmc-M150-B50.dtsi" /include/ "product/hi1910B-i2c-M150-B50.dtsi" /include/ "product/hi1910B-spi-M150-B50.dtsi"
cd product
vim hi1910B-pcie-rc-M150-B50.dtsi
lan_index |
控制器 |
---|---|
lane0~lane1 |
PCIe控制器0 |
lane2~lane3 |
PCIe控制器1 |
lane4~lane5 |
PCIe控制器2 |
lane6~lane7 |
PCIe控制器3 |
以7.c中serdes_info配置为例,共使用了PCIe控制器0、PCIe控制器1,则在PCIe的.dtsi文件中保留PCIe控制器0、PCIe控制器1两个控制器的配置,将PCIe控制器2、PCIe控制器3的配置代码注释即可,其中/*和*/代表注释代码段,具体修改如下所示。
pcie@0x820000000 { compatible = "pci-host-ecam-generic"; // ECAM 0x820000000 pci host bridge0 // reg = <0x8 0x20000000 0 0x00400000>; reg-names = "ecam-cfg"; bus-range = <0x0 0x3>; msi-map = <0x0 &its 0x0 0x2000>; msi-map-mask = <0xffff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; // BAR MAP: 32bit mem 64M, 64bit mem 256M // ranges = <0x02000000 0x0 0xB0000000 0x0 0xB0000000 0x0 0x04000000 0x43000000 0x8 0x30000000 0x8 0x30000000 0x0 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0xf800 0 0 0x7>; // INTX // interrupt-map = <0x4000 0 0 1 &mbigen_pcie0_local 704 4 0x4000 0 0 2 &mbigen_pcie0_local 705 4 //PCIe控制器0 0x4000 0 0 3 &mbigen_pcie0_local 706 4 0x4000 0 0 4 &mbigen_pcie0_local 707 4>; iommu-map = <0 &io_smmu 0 0x400>; status = "ok"; }; pcie@0x840000000 { compatible = "pci-host-ecam-generic"; pcie-core-id = <1>; // ECAM 0x840000000 pci host bridge0 reg = <0x8 0x40400000 0 0x00400000>; reg-names = "ecam-cfg"; bus-range = <0x4 0x7>; msi-map = <0x400 &its 0x400 0x2000>; msi-map-mask = <0xffff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; // BAR MAP: 32bit mem 64M, 64bit mem 256M ranges = <0x02000000 0x0 0xB4000000 0x0 0xB4000000 0x0 0x04000000 0x43000000 0x8 0x50000000 0x8 0x50000000 0x0 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0xff0000 0 0 0x7>; // INTX interrupt-map = <0x40000 0 0 1 &mbigen_pcie1_local 712 4 0x40000 0 0 1 &mbigen_pcie1_local 713 4 //PCIe控制器1 0x40000 0 0 1 &mbigen_pcie1_local 714 4 0x40000 0 0 1 &mbigen_pcie1_local 715 4>; iommu-map = <0x400 &io_smmu 0x400 0x400>; status = "ok"; }; /* pcie@0x860000000 { compatible = "pci-host-ecam-generic"; // ECAM 0x860000000 pci host bridge0 // reg = <0x8 0x60800000 0 0x00400000>; reg-names = "ecam-cfg"; bus-range = <0x8 0xb>; msi-map = <0x800 &its 0x800 0x2000>; msi-map-mask = <0xffff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; // BAR MAP: 32bit mem 64M, 64bit mem 256M // ranges = <0x02000000 0x0 0xB8000000 0x0 0xB8000000 0x0 0x04000000 0x43000000 0x8 0x70000000 0x8 0x70000000 0x0 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0xf800 0 0 0x7>; // INTX // interrupt-map = <0x4000 0 0 1 &mbigen_pcie2_local 720 4 0x4000 0 0 2 &mbigen_pcie2_local 721 4 //PCIe控制器2 0x4000 0 0 3 &mbigen_pcie2_local 722 4 0x4000 0 0 4 &mbigen_pcie2_local 723 4>; iommu-map = <0x800 &io_smmu 0x800 0x400>; status = "ok"; }; */ /* pcie@0x900000000 { compatible = "pci-host-ecam-generic"; pcie-core-id = <3>; // ECAM 0x900000000 pci host bridge0 reg = <0x9 0x00c00000 0 0x00400000>; reg-names = "ecam-cfg"; bus-range = <0xc 0xf>; msi-map = <0xc00 &its 0xc00 0x2000>; msi-map-mask = <0xffff>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; dma-coherent; // BAR MAP: 32bit mem 64M, 64bit mem 256M ranges = <0x02000000 0x0 0xBC000000 0x0 0xBC000000 0x0 0x04000000 0x43000000 0x9 0x10000000 0x9 0x10000000 0x0 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0xff0000 0 0 0x7>; // INTX interrupt-map = <0xc0000 0 0 1 &mbigen_pcie3_local 728 4 0xc0000 0 0 1 &mbigen_pcie3_local 729 4 //PCIe控制器3 0xc0000 0 0 1 &mbigen_pcie3_local 730 4 0xc0000 0 0 1 &mbigen_pcie3_local 731 4>; iommu-map = <0xc00 &io_smmu 0xc00 0x400>; status = "ok"; }; */
set(DTS_BASE_DIR ${TOP_DIR}/tools/customize/dts) if(PRODUCT STREQUAL "ascend310Besl" OR PRODUCT STREQUAL "ascend310B" OR PRODUCT STREQUAL "ascend310Bemu" OR PRODUCT STREQUAL "ascend310Brc" OR PRODUCT STREQUAL "ascend310Brcesl" OR PRODUCT STREQUAL "ascend310Brcemu") # 当前driver跟esl用相同的dts,后期需要更新到单独的目录 set(DTS_SRC_DIR ${DTS_BASE_DIR}/hi1910b/hi1910BL) set(DTS_FILE_LIST hi1910B-default.dts unreleased/hi1911-esl/hi1911-esl-b600.dts unreleased/hi1911-esl/hi1911-esl-rc-b600.dts unreleased/hi1911-fpga/hi1911-fpga-b600_b0.dts unreleased/hi1911-fpga/hi1911-fpga-b600_b0_b1.dts unreleased/hi1911-fpga/hi1911-fpga-b600_b0_b2.dts unreleased/hi1911-fpga/hi1911-fpga-rc-b600_b0.dts unreleased/hi1911-fpga/hi1911-fpga-rc-b600_b0_b1.dts unreleased/hi1911-fpga/hi1911-fpga-rc-b600_b0_b2.dts hi1910B-evb-900.dts hi1910B-evb-901.dts hi1910B-evb-902.dts hi1910B-evb-903.dts hi1910B-evb-905.dts hi1910B-asic-M150-B50.dts hi1910B-asic-M100-B51.dts hi1910B-asic-M150-B51.dts hi1910B-asic-M160-B51.dts hi1910B-asic-M100-B00.dts hi1910B-asic-M101-B00.dts hi1910B-asic-M150-B00.dts hi1910B-asic-M151-B00.dts hi1910B-asic-M150-B33.dts)
新增加的dts只能在加粗字体段落末尾添加。
具体串口日志如下图所示。
su - root
reboot
建议查看串口日志确认升级重启进展。
以连接SATA硬盘为例,将配套的SATA硬盘连接到Atlas 200I A2 加速模块的底板上。
lsblk
显示硬盘详细信息,如显示类似容量、厂家信息等即表示硬盘在位。SATA接口通信正常。